Flip-flops are often used by system designers to synchronize signals operating at different frequencies to a local clock. However, since the signals are asynchronous to the local clock, the setup and hold time specifications associated with the flip-flop are sure to be violated. When the setup and hold time is violated, the output response of the flip-flop is uncertain. The output may assume a "metastable" state, defined as the time period during which the output of a digital logic device is not at logic level 1 or logic level 0, but instead resides at an output level between logic level 0 and logic level 1. The voltage ranges corresponding to different logic levels are specified by the manufacturer of the device. For bipolar TTL technology, for example, the metastable region might lie between 0.8 volts and 2.0 volts.
The metastable problem occurs when the signal being input to the flip-flop is undergoing a transition from one logic level to the other simultaneously with the active edge of the local clock pulse, causing the latch section of the flip-flop to latch at the intermediate voltage level. Since the input data is changing while it is being clocked, the system designer does not care if the flip-flop goes to either a high or low logic level in this instance, just so long as the output does not "hang-up" in the metastable region. Eventually, the output of the flip-flop will stabilize at a valid logic level; however, logic circuitry following the flip-flop depends upon the delay specification (stated time period from the clock pulse to a valid output) being met. A metastable output may cause this logic circuitry to fail. Thus, the metastable characteristics of the flip-flop used to synchronize an asynchronous data stream can influence overall system reliability.
One attempt to mitigate the problem of metastable outputs is to provide a second flip-flop in series with the first flip-flop. The clock to the second flip-flop is delayed relative to clock to the first flip-flop, thus allowing time for the output signal of the first flip-flop to stabilize at a valid logic level before clocking the data into the second flip-flop. Using a dual flip-flop system, the delay from input-to-valid output includes the delay through each of the flip-flops, plus the delay between the clocks to the flip-flops. In many applications, this delay is excessive. Furthermore, the logic may still fail if the output of the first flip-flop remains in the metastable region for a period greater than the delay between the clocks.
Therefore, a need has arisen for a flip-flop circuit which reduces the probability of metastable outputs, without introducing excessive delays, and is adapted for implementation in a single, integrated circuit.